Embodiments disclosed in the present invention relate generally to electrical technology, and more specifically to a semiconductor component and method of fabricating the same.
For certain applications it is desirable to package multiple semiconductor integrated circuits (IC's), components, chips or die in a single package. For example, in a battery protection circuit application, a power control IC and two metal oxide semiconductor field effect transistors (MOSFETs) are packaged together in a lead frame package. The best performance for the battery protection package is achieved by using the largest possible MOSFET size to minimize the drain to source turn-on resistance (Rds-on). However, a smaller overall size of the packaged IC's is desirable to accommodate ever shrinking electronic devices. To achieve a smaller footprint for multiple die in a single package, the die have been stacked on each other where possible.
Stacking of die on each other does, however, create challenges in the manufacturing and reliability of the package. In addition, along with the demands to shrink electronic devices there is also an ever present demand to improve the manufacturing of any integrated circuit packages. Accordingly, it would be desirable to develop a stacked die package having improved manufacturability and reliability.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description.